Groups Search groups. Log in Register. Search only containers. Search titles only. Search Advanced search…. New posts. Search forums. Log in. Install the app. Contact us. Close Menu. Welcome to EDAboard. The clock buffers are designed with some special property like high drive strength, equal rise and fall time, less delay and less delay variation with PVT and OCV.
Clock buffer has an equal rise and fall time. This prevents the duty cycle of clock signal from changing when it passes through a chain of clock buffers. How to decide whether we need to used buffer or inverter for building a clock tree in the clock tree synthesis stage. This decision totally depends on the libraries which we are using. The main factors which we consider to choose inverter or buffer are rise delay, fall delay, drive strength and insertion delay latency of the cell.
In most of the library files, a buffer is the combination of two inverters so we can say that inverter will be having lesser delay than buffer with the same drive strength. Clock buffers sometimes have input and output pins on higher metal layers much fewer vias are needed in the clock distribution root. Normal buffer has pins on lower metal layers like metal1. Some lib also has clock buffers with input pins on high metal layers and output pins on lower metal layers.
Normally clock routing is done into higher metal layers as compared to signal routing so to provide easier access to clock pins from these layers clock buffer may have pins in higher metal layers. And for normal buffer pins may be in lower metal layers. Clock buffer are balanced i. If these are not equal then duty cycle distortion in the clock tree will occur and because of this minimum pulse width violation comes into the picture. On the other hand normal buffer have not equal rise and fall time.
The advantage of using an inverter-based tree is that it gives equal rise and fall transition so due to that jitter duty cycle jitter get canceled out and we get symmetrical high and low pulse width. Buffer contain two inverters with unequal size in area and unequal drive strength. First inverter is of small size having low drive strength and the second buffer is of large size having high drive, strength are connected back to back as shown in figure below.
So a load of these two inverters are unequal. So mainly we are preferred inverter-based trees instead of the buffer based. Clock buffer is typically used to fan out clock signal and isolate the source from the loads. The clock generator gives great flexibility to system designer. The buffer, though, can not be used as a generator. Site Search User. Mentions Tags More Cancel. Ask a related question What is a related question? In other words, rise and fall times of clock buffers are nearly equal.
The reason behind this is that if the clock buffers are not balanced, there will be duty cycle distortion in the clock tree, which can lead to pulse width violations as discussed in minimum pulse width violation example. Due to above reason, clock buffers consume more power as compared to normal buffers. Generally, you will find clock buffers with higher drive strength as compared to normal buffers. So that a clock buffer can drive long nets and can have higher fanouts. This helps clock buffers, and hence, clock trees to have less overall delays.
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